PIC10F320T-EMCSQTP datasheet(13/210 Pages) MICROCHIP

13 / 210 page

 2011 Microchip Technology Inc.

Preliminary

DS41585A-page 13

PIC10(L)F320/322

2.2

Data Memory Organization

The data memory is in one bank, which contains the

General Purpose Registers (GPR) and the Special

Function Registers (SFR). The RP<1:0> bits of the

STATUS register are the bank select bits.

RP1 RP0

 Bank 0 is selected

The bank extends up to 7Fh (128 bytes). The lower

locations of the bank are reserved for the Special Func-

tion Registers. Above the Special Function Registers

are the General Purpose Registers, implemented as

Static RAM.

2.2.1

GENERAL PURPOSE REGISTER

FILE

The register file is organized as 64 x 8 in the

PIC10(L)F320/322. Each register is accessed, either

directly or indirectly, through the File Select Register

(FSR) (see Section 2.4 “Indirect Addressing, INDF

and FSR Registers”

2.2.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and peripheral functions for controlling the

desired operation of the device (see Table 2-3). These

registers are static RAM.

The special registers can be classified into two sets:

core and peripheral. The Special Function Registers

associated with the “core” are described in this section.

Those related to the operation of the peripheral features

are described in the section of that peripheral feature.

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