MPC8360CVVALDHA datasheet(83/102 Pages) FREESCALE

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MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

Freescale Semiconductor

System PLL Configuration

ordered, see Section 24.1, “Part Numbers Fully Addressed by this Document,” for part ordering details and contact your

Freescale sales representative or authorized distributor for more information.

21.1

System PLL Configuration

The system PLL is controlled by the RCWL[SPMF] and RCWL[SVCOD] parameters. This table shows the multiplication

factor encodings for the system PLL.

Table 69. Operating Frequencies for the TBGA Package

Characteristic1

400 MHz

533 MHz

667 MHz2

Unit

e300 core frequency (core_clk)

266–400

266–533

266–667

MHz

Coherent system bus frequency (csb_clk)

133–333

MHz

QUICC Engine frequency3 (ce_clk)

266–500

MHz

DDR and DDR2 memory bus frequency (MCLK)4

100–166.67

MHz

Local bus frequency (LCLKn)5

16.67–133

MHz

PCI input frequency (CLKIN or PCI_CLK)

25–66.67

MHz

Security core maximum internal operating frequency

133

166

MHz

Notes:

1. The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk,

MCLK, LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.

2. The 667 MHz core frequency is based on a 1.3 V VDD supply voltage.

3. The 500 MHz QE frequency is based on a 1.3 V VDD supply voltage.

4. The DDR data rate is 2x the DDR memory bus frequency.

5. The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1× or 2×

the csb_clk frequency (depending on RCWL[LBCM]).

Table 70. System PLL Multiplication Factors

RCWL[SPMF]

System PLL

Multiplication Factor

0000

× 16

0001

Reserved

0010

× 2

0011

× 3

0100

× 4

0101

× 5

0110

× 6

0111

× 7

1000

× 8

1001

× 9

1010

× 10

1011

× 11

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