MPC8360CVVALDHA datasheet(82/102 Pages) FREESCALE

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MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5

Freescale Semiconductor

Pinout Listings

clock. When the device is configured as a PCI agent device the CLKIN and the CFG_CLKIN_DIV signals should be tied to

GND.

When the device is configured as a PCI host device (RCWH[PCIHOST] = 1) and PCI clock output is disabled

(RCWH[PCICKDRV] = 0), clock distribution and balancing done externally on the board. Therefore, PCI_SYNC_IN is the

primary input clock.

As shown in Figure 54 and Figure 55, the primary clock input (frequency) is multiplied by the QUICC Engine block

phase-locked loop (PLL), the system PLL, and the clock unit to create the QUICC Engine clock (ce_clk), the coherent system

bus clock (csb_clk), the internal DDRC1 controller clock (ddr1_clk), and the internal clock for the local bus interface unit and

DDR2 memory controller (lb_clk).

The csb_clk frequency is derived from a complex set of factors that can be simplified into the following equation:

csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF

In PCI host mode, PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is the CLKIN frequency; in PCI agent mode, CFG_CLKIN_DIV

must be pulled down (low), so PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is the PCI_CLK frequency.

The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies up the csb_clk frequency

to create the internal clock for the e300 core (core_clk). The system and core PLL multipliers are selected by the SPMF and

COREPLL fields in the reset configuration word low (RCWL) which is loaded at power-on reset or by one of the hard-coded

reset options. See Chapter 4, “Reset, Clocking, and Initialization,” in the MPC8360E PowerQUICC II Pro Integrated

Communications Processor Reference Manual for more information on the clock subsystem.

The ce_clk frequency is determined by the QUICC Engine PLL multiplication factor (RCWL[CEPMF) and the QUICC Engine

PLL division factor (RCWL[CEPDF]) according to the following equation:

ce_clk = (primary clock input × CEPMF)

÷ (1 + CEPDF)

The internal ddr1_clk frequency is determined by the following equation:

ddr1_clk = csb_clk × (1 + RCWL[DDR1CM])

Note that the lb_clk clock frequency (for DDRC2) is determined by RCWL[LBCM]. The internal ddr1_clk frequency is not the

external memory bus frequency; ddr1_clk passes through the DDRC1 clock divider (

÷2) to create the differential DDRC1

memory bus clock outputs (MEMC1_MCK and MEMC1_MCK). However, the data rate is the same frequency as ddr1_clk.

The internal lb_clk frequency is determined by the following equation:

lb_clk = csb_clk × (1 + RCWL[LBCM])

Note that lb_clk is not the external local bus or DDRC2 frequency; lb_clk passes through the a LB clock divider to create the

external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LB clock divider ratio is controlled by LCRR[CLKDIV].

Additionally, some of the internal units may be required to be shut off or operate at lower frequency than the csb_clk frequency.

Those units have a default clock ratio that can be configured by a memory mapped register after the device comes out of reset.

This table specifies which units have a configurable clock frequency.

This table provides the operating frequencies for the TBGA package under recommended operating conditions (see Table 2).

All frequency combinations shown in the table below may not be available. Maximum operating frequencies depend on the part

Table 68. Configurable Clock Units

Unit

Default

Frequency

Options

Security core

csb_clk/3

Off,

csb_clk1, csb_clk/2,

csb_clk/3

1 With limitation, only for slow csb_clk rates, up to 166 MHz.

PCI and DMA complex

csb_clk

Off,

csb_clk

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