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PCIF0 Folha de dados(PDF) 58 Page - ATMEL Corporation

Nome de Peças PCIF0
Descrição Electrónicos  High Performance, Low Power Atmel AVR 8-bit Microcontroller Advanced RISC Architecture
PDF  294 Pages
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Fabricante Electrônico  ATMEL [ATMEL Corporation]
Página de início  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

PCIF0 Folha de dados(HTML) 58 Page - ATMEL Corporation

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58
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
Figure 6-7.
Watchdog Timer
The WDT gives an interrupt or a system reset when the counter reaches a given time-out
value. In normal operation mode, it is required that the system uses the WDR - Watchdog
Timer Reset - instruction to restart the counter before the time-out value is reached. If the sys-
tem doesn't restart the counter, an interrupt or system reset will be issued.
In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be
used to wake the device from sleep-modes, and also as a general system timer. One example
is to limit the maximum time allowed for certain operations, giving an interrupt when the opera-
tion has run longer than expected. In System Reset mode, the WDT gives a reset when the
timer expires. This is typically used to prevent system hang-up in case of runaway code. The
third mode, Interrupt and System Reset mode, combines the other two modes by first giving
an interrupt and then switch to System Reset mode. This mode will for instance allow a safe
shutdown by saving critical parameters before a system reset.
The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to
System Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Inter-
rupt mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security,
alterations to the Watchdog set-up must follow timed sequences. The sequence for clearing
WDE and changing time-out configuration is as follows:
1.
In the same operation, write a logic one to the Watchdog change enable bit (WDCE)
and WDE. A logic one must be written to WDE regardless of the previous value of the
WDE bit.
2.
Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP)
as desired, but with the WDCE bit cleared. This must be done in one operation.
MCU
RESET
WATCHDOG
RESET
CLOCK
MONITORING
INTERRUPT
WDE
WDIF
WDIE
WDP0
WDP1
WDP2
WDP3
WATCHDOG
PRESCALER
~128 KHz
OSCILLATOR



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