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PCIF0 Folha de dados(PDF) 36 Page - ATMEL Corporation

Nome de Peças PCIF0
Descrição Electrónicos  High Performance, Low Power Atmel AVR 8-bit Microcontroller Advanced RISC Architecture
PDF  294 Pages
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Fabricante Electrônico  ATMEL [ATMEL Corporation]
Página de início  http://www.atmel.com
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PCIF0 Folha de dados(HTML) 36 Page - ATMEL Corporation

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36
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
–‘Recover System Clock Source’,
–‘Enable Watchdog in Automatic Reload Mode’.
• Command status return. The ‘Request Clock Availability ’ command returns status via the
CLKRDY bit in the CLKCSR register. The ‘Recover System Clock Source ’ command
returns a code of the current clock source in the CLKSELR register. This information is
used in the supervisory software routines as shown in Section 4.3.7 on page 37.
4.3.2
CLKSELR Register
4.3.2.1
Fuses Substitution
At reset, bits of the Low Fuse Byte are copied into the CLKSELR register. The content of this
register can subsequently be user modified to overwrite the default values from the Low Fuse
Byte. CKSEL3..0, SUT1..0 and CKOUT fuses correspond respectively to CSEL3..0, CSUT1:0
and ~(COUT) bits of the CLKSELR register as shown in Figure 4-5 on page 36.
4.3.2.2
Source Selection
The available codes of clock source are given in Table 4-1 on page 29.
Figure 4-5.
Fuses substitution and Clock Source Selection
The CLKSELR register contains the CSEL, CSUT and COUT values which will be used by the
‘Enable/Disable Clock Source’, ‘Request for Clock Availability’ or ‘Clock Source Switching’
commands.
4.3.2.3
Source Recovering
The ‘Recover System Clock Source’ command updates the CKSEL field of CLKSELR register
(See “System Clock Source Recovering” on page 37.).
4.3.3
Enable/Disable Clock Source
The ‘Enable Clock Source’ command selects and enables a clock source configured by the
settings in the CLKSELR register. CSEL3..0 will select the clock source and CSUT1:0 will
select the start-up time (just as CKSEL and SUT fuse bits do). To be sure that a clock source
is operating, the ‘Request for Clock Availability ’ command must be executed after the ‘Enable
Register:
CLKSELR
Fuse:
Fuse Low Byte
SEL-1
SEL-0
SEL-2
SEL-n
CKSEL[3..0]
SUT[1..0]
EN-1
EN-0
EN-2
EN-n
CKOUT
Reset
SCLKRq
(*)
SCLKRq
(*): Command of Clock Control & Status Register
Selected
Configuration
Clock
Switch
Current
Configuration



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