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PCIF0 Folha de dados(PDF) 267 Page - ATMEL Corporation |
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PCIF0 Folha de dados(HTML) 267 Page - ATMEL Corporation |
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267 / 294 page ![]() 267 9219A–RFID–01/11 Atmel ATA5505 [Preliminary] 23.11 SPI Timing Characteristics See Figure 23-6 and Figure 23-7 for details. Note: In SPI Programming mode the minimum SCK high/low period is: - 2 t CLCL for fCK < 12MHz - 3 tCLCL for fCK >12MHz Figure 23-6. SPI Interface Timing Requirements (Master Mode) Table 23-12. SPI Timing Parameters Description Mode Min. Typ. Max. 1 SCK period Master See Table 13-4 ns 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.5 • t sck 7 SCK to out Master 10 8 SCK to out high Master 10 9 SS low to out Slave 15 10 SCK period Slave 4 • t ck 11 SCK high/low (1) Slave 2 • tck 12 Rise/Fall time Slave 1.6 µs 13 Setup Slave 10 ns 14 Hold Slave tck 15 SCK to out Slave 15 16 SCK to SS high Slave 20 17 SS high to tri-state Slave 10 18 SS low to SCK Slave 2 • t ck MOSI (Data Output) SCK (CPOL = 1) MISO (Data Input) SCK (CPOL = 0) SS MSB LSB LSB MSB ... ... 61 22 3 45 8 7 |
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