PCIF0 datasheet(231/294 Pages) ATMEL

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231

9219A–RFID–01/11

Atmel ATA5505 [Preliminary]

• Bit 0 – SPMEN: Self Programming Enable

This bit enables the SPM instruction for the next four clock cycles. If written to one together

with either SIGRD, CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have

a special meaning, see description above. If only SPMEN is written, the following SPM instruc-

tion will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The

LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM

instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase

and Page Write, the SPMEN bit remains high until the operation is completed.

Writing any other combination than “10 0001

b”, “01 0001 b”, “00 1001 b”, “00 0101 b”,

“00 0011

b” or “00 0001 b” in the lower six bits will have no effect.

Note:

Only one SPM instruction should be active at any time.

21.2.2

EEPROM Write Prevents Writing to SPMCSR

Note that an EEPROM write operation will block all software programming to Flash. Reading

the Fuses and Lock bits from software will also be prevented during the EEPROM write opera-

tion. It is recommended that the user checks the status bit (EEPE) in the EECR Register and

verifies that the bit is cleared before writing to the SPMCSR Register.

21.2.3

Reading the Fuse and Lock Bits from Software

It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the

Z-pointer with 0x0001 and set the RFLB and SPMEN bits in SPMCSR. When an LPM instruc-

tion is executed within three CPU cycles after the RFLB and SPMEN bits are set in SPMCSR,

the value of the Lock bits will be loaded in the destination register. The RFLB and SPMEN bits

will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed

within three CPU cycles or no SPM instruction is executed within four CPU cycles. When

RFLB and SPMEN are cleared, LPM will work as described in the Instruction set Manual.

The algorithm for reading the Fuse Low byte is similar to the one described above for reading

the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the RFLB

and SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after

the RFLB and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will

be loaded in the destination register as shown below. See Table 22-5 on page 238 for a

detailed description and mapping of the Fuse Low byte.

Similarly, when reading the Fuse High byte (FHB), load 0x0003 in the Z-pointer. When an

LPM instruction is executed within three cycles after the RFLB and SPMEN bits are set in the

SPMCSR, the value of the Fuse High byte will be loaded in the destination register as shown

below. See Table 22-4 on page 237 for detailed description and mapping of the Fuse High

byte.

Bit

Rd (Z=0x0001)

––

LB2

LB1

Bit

765

321

Rd (Z=0x0000)

FLB7

FLB6

FLB5

FLB4

FLB3

FLB2

FLB1

FLB0

Bit

765

3210

Rd (Z=0x0003)

FHB7

FHB6

FHB5

FHB4

FHB3

FHB2

FHB1

FHB0

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