PCIF0 datasheet(224/294 Pages) ATMEL

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224

9219A–RFID–01/11

Atmel ATA5505 [Preliminary]

Note:

When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by

clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when

the bits are changed.

19.1.3

DIDR0 – Digital Input Disable Register 0

• Bits 7,6 – AIN1D, AIN0D: AIN1D and AIN0D Digital Input Disable

When this bit is written logic one, the digital input buffer on the corresponding Analog Com-

pare pin is disabled. The corresponding PIN register bit will always read as zero when this bit

is set. When an analog signal is applied to the AIN0/1 pin and the digital input from this pin is

not needed, this bit should be written logic one to reduce power consumption in the digital

input buffer.

19.2

Analog Comparator Inputs

19.2.1

Analog Compare Positive Input

It is possible to select any of the inputs of the ADC Positive Input Multiplexer to replace the

positive input to the Analog Comparator. The ADC multiplexer is used to select this input, and

consequently, the ADC must be switched off to utilize this feature. If the Analog Comparator

Multiplexer Enable bit (ACME in ADCSRB register) is set and the ADC is switched off (ADEN

in ADCSRA register is zero), MUX[4..0] in ADMUX register select the input pin to replace the

positive input to the Analog Comparator, as shown in Table 19-2. If ACME is cleared or ADEN

is set, AIN1 pin is applied to the positive input to the Analog Comparator.

Table 19-1.

ACIS1 / ACIS0 Settings

ACIS1

ACIS0

Interrupt Mode

Comparator Interrupt on Output Toggle.

Reserved

Comparator Interrupt on Falling Output Edge.

Comparator Interrupt on Rising Output Edge.

Bit

543210

ADC7D /

AIN1D

ADC6D /

AIN0D

ADC5D

ADC4D

ADC3D

ADC2D

ADC1D

ADC0D

DIDR0

Read/Write

R/W

Initial Value

000000

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