PCIF0 datasheet(176/294 Pages) ATMEL

176 / 294 page

176

9219A–RFID–01/11

Atmel ATA5505 [Preliminary]

The re-synchronization implemented in the controller tolerates a clock deviation of ± 20% and

adjusts the baud rate in a ± 2% range.

The new LBT[5..0] value will be used up to the end of the response. Then, the LBT[5..0] will be

reset to 32 for the next header.

The LINBTR register can be used to (software) re-calibrate the clock oscillator.

The re-synchronization is not performed if the LIN node is enabled as a master.

15.5.6.3

Handling LBT[5..0]

LDISR bit of LINBTR register is used to:

• Disable the re-synchronization (for instance in the case of LIN MASTER node),

• To enable the setting of LBT[5..0] (to manually adjust the baud rate especially in the case of

UART mode). A minimum of 8 is required for LBT[5..0] due to the sampling operation.

Note that the LENA bit of LINCR register is important for this handling (see Figure 15-8 on

page 176).

Figure 15-8. Handling LBT[5..0]

15.5.7

Data Length

Section 15.4.6 “LIN Commands” on page 170 describes how to set or how are automatically

set the LRXDL[3..0] or LTXDL[3..0] fields of LINDLR register before receiving or transmitting a

response.

In the case of Tx Response the LRXDL[3..0] will be used by the hardware to count the number

of bytes already successfully sent.

In the case of Rx Response the LTXDL[3..0] will be used by the hardware to count the number

of bytes already successfully received.

If an error occurs, this information is useful to the programmer to recover the LIN messages.

15.5.7.1

Data Length in LIN 2.1

• If LTXDL[3..0]=0 only the CHECKSUM will be sent,

• If LRXDL[3..0]=0 the first byte received will be interpreted as the CHECKSUM,

• If LTXDL[3..0] or LRXDL[3..0] >8, values will be forced to 8 after the command setting and

before sending or receiving of the first byte.

Write in LINBTR register

LENA ?

(LINCR bit 4)

LDISR

to write

LBT[5..0] forced to 0x20

LDISR forced to 0

Enable re-synch. in LIN mode

LBT[5..0] = LBT[5..0] to write

(LBT[5..0]min=8)

LDISR forced to 1

Disable re-synch. in LIN mode

PCIF0 Folha de dados(PDF) 176 Page - ATMEL Corporation

PCIF0 Folha de dados(HTML) 176 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL