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PCIF0 Folha de dados(PDF) 165 Page - ATMEL Corporation

Nome de Peças PCIF0
Descrição Electrónicos  High Performance, Low Power Atmel AVR 8-bit Microcontroller Advanced RISC Architecture
PDF  294 Pages
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Fabricante Electrônico  ATMEL [ATMEL Corporation]
Página de início  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

PCIF0 Folha de dados(HTML) 165 Page - ATMEL Corporation

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9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
15. LIN / UART - Local Interconnect Network Controller or UART
The LIN (Local Interconnect Network) is a serial communications protocol which efficiently
supports the control of mechatronics nodes in distributed automotive applications. The main
properties of the LIN bus are:
• Single master with multiple slaves concept
• Low cost silicon implementation based on common UART/SCI interface
• Self synchronization with on-chip oscillator in slave node
• Deterministic signal transmission with signal propagation time computable in advance
• Low cost single-wire implementation
• Speed up to 20 Kbit/s.
LIN provides a cost efficient bus communication where the bandwidth and versatility of CAN
are not required. The specification of the line driver/receiver needs to match the ISO9141
NRZ-standard.
If LIN is not required, the controller alternatively can be programmed as Universal Asynchro-
nous serial Receiver and Transmitter (UART).
15.1
LIN Features
• Hardware Implementation of LIN 2.1 (LIN 1.3 Compatibility)
• Small, CPU Efficient and Independent Master/Slave Routines Based on “LIN Work Flow
Concept” of LIN 2.1 Specification
• Automatic LIN Header Handling and Filtering of Irrelevant LIN Frames
• Automatic LIN Response Handling
• Extended LIN Error Detection and Signaling
• Hardware Frame Time-out Detection
• “Break-in-data” Support Capability
• Automatic Re-synchronization to Ensure Proper Frame Integrity
• Fully Flexible Extended Frames Support Capabilities
15.2
UART Features
• Full Duplex Operation (Independent Serial Receive and Transmit Processes)
• Asynchronous Operation
• High Resolution Baud Rate Generator
• Hardware Support of 8 Data Bits, Odd/Even/No Parity Bit, 1 Stop Bit Frames
• Data Over-Run and Framing Error Detection



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