SPIRIT1 datasheet(37/94 Pages) STMICROELECTRONICS

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SPIRIT1

Block description

Doc ID 022758 Rev 3

37/94

without any risk of glitches in the digital clock is to switch into STANDBY mode, hence, reset

the bit-field PD_CLKDIV in the XO_RCO_TEST register, and then come back to the READY

state. Also the synthesizer reference signal can be divided by 2, setting the bit-field REFDIV

in the SYNTH_CONFIG register.

The integrated phase locked loop (PLL) is capable of synthesizing the frequencies in the

bands from 169.1 to 169.5, from 300 to 348 MHz, from 387 to 470 MHz, or from 779 to 956

MHz, providing the LO signal for the RX chain and the input signal for the PA in the TX

chain.

Frequency tolerance and startup times depend on the crystal used, although some tuning of

the latter parameter is possible through the GM_CONF field of the ANA_FUNC_CONF

registers.

Depending on the RF frequency and channel spacing, a very high accurate crystal or TCXO

can be required.

The RF synthesizer implements fractional sigma delta architecture to allow fast settling and

narrow channel spacing. It is fully integrated and uses a multi-band VCO to cover the whole

frequency range. All internal calibrations are performed automatically.

The PLL output frequency can be configured by programming the SYNT field of the SYNT3,

SYNT2, SYNT1, and SYNT0 registers and BS field of the SYNT0 register (see

Section 9.5.2). The user must configure these registers according to the effective reference

frequency in use (24 MHz, 26 MHz, 48 MHz, or 52 MHz). In the latter two cases, the user

must enable the frequency divider by 2 for the digital clock, in order to run the digital macro

at a lower frequency. The configuration bit for the digital clock divider is inside the

XO_RCO_TEST register (default case is divider enabled). In addition, the user can also

enable a divider by 2 applied to the reference clock. The configuration bit for the reference

clock divider is inside the SYNTH_CONFIG[1] register. The user must select a 3-bit word in

order to set the charge pump current according to the LO frequency variations, in order to

have a constant loop bandwidth. This can be done by writing the WCP field of the SYNT3

Table 21.

Programmability of trans-conductance at startup

GM_CONF[2:0]

Gm at startup [ms]

000

13.2

001

18.2

010

21.5

011

25.6

100

28.8

101

33.9

110

38.5

111

43.0

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