SPIRIT1 datasheet(36/94 Pages) STMICROELECTRONICS

36 / 94 page

Block description

SPIRIT1

36/94

Doc ID 022758 Rev 3

Block description

8.1

Power management

The SPIRIT1 integrates a high efficiency step-down converter cascaded with LDOs meant

to supply both analog and digital parts. However, an LDO directly fed by the external battery

provides a controlled voltage to the data interface block.

8.2

Power-on-reset (POR)

The power-on-reset circuit generates a reset pulse upon power-up which is used to initialize

the entire digital logic. Power-on-reset senses VBAT voltage.

8.3

Low battery indicator

The battery indicator can provide the user with an indication of the battery voltage level.

There are two blocks to detect battery level:

●

Brownout with a fixed threshold as defined inTable 16: Battery indicator and low battery

detector

●

Battery level detector with a programmable threshold as defined in Table 16: Battery

indicator and low battery detector.

Both blocks can be optionally activated to provide the MCU with an early warning of

impending power failure. It does not reset the system, but gives the MCU time to prepare for

an orderly power-down and provides hardware protection of data stored in the program

memory, by preventing write instructions being executed.

The low battery indicatorr function is available in any of the SPIRIT1 operation modes. As

this function requires the internal bias circuit operation, the overall current consumption in

STANDBY, SLEEP, and READY modes is increased by 400 µA.

8.4

Voltage reference

This block provides the precise reference voltage needed by the internal circuit.

8.5

Oscillator and RF synthesizer

A crystal connected to XIN and XOUT is used to provide a clock signal to the frequency

synthesizer. The allowed clock signal frequency is either 24, 26, 48, or 52 MHz. As an

alternative, an external clock signal can be used to feed XIN for proper operation. In this

option, XOUT can be left either floating or tied to ground.

Since the digital macro cannot be clocked at that double frequency (48 MHz or 52 MHz), a

divided clock is used in this case.

The digital clock divider is enabled by default and must be kept enabled if the crystal is in the

(48 - 52) MHz range; if the crystal is in the (24 - 26) MHz range, then the divider must be

disabled before starting any TX/RX operation. The safest procedure to disable the divider

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