SPIRIT1 datasheet(75/94 Pages) STMICROELECTRONICS

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SPIRIT1

Doc ID 022758 Rev 3

75/94

MCU_CK_CONF

0x06

EN_MCU_CLK

R/W

1: The internal divider logic is

running, so the MCU clock is

available (but proper GPIO

configuration is needed)

6:5

CLOCK_TAIL[1:0]

Number of extra clock cycles

provided to the MCU before

switching to STANDBY state:

00: 0 extra clock cycle

01: 64 extra clock cycles

10: 256 extra clock cycles

11: 512 extra clock cycles

4:1

XO_RATIO[3:0]

Divider for the XO clock output

RCO_RATIO

Divider for the RCO clock

output

0: 1

1: 1/128

XO_RCO_TEST

0xB4

7:4

Reserved

3PD_CLKDIV

1: disable both dividers of the

digital clock (and reference

clock for the SMPS) and IF-

ADC clock.

2:0

Reserved

SYNTH_CONFIG[0]

0x9F

SEL_TSPLIT

R/W

0: split time: 1.75 ns

1: split time: 3.47 ns

6:0

Reserved

SYNTH_CONFIG[1]

0x9E

7REFDIV

R/W

Enable division by 2 on the

reference clock:

0: fREF = fXO frequency

1: fREF = fXO frequency / 2

6:3

Reserved

VCO_L_SEL

1: enable the VCO_L

VCO_H_SEL

1: enable the VCO_L

Reserved

IF_OFFSET_ANA

0x07

7:0

IF_OFFSET_ANA

0xA3

R/W

Intermediate frequency setting

for the analog RF synthesizer.

(see Section 9.4)

Table 37.

General configuration registers (continued)

Address

Bit

Field name

Reset

R/W

Description

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