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AS8650 Folha de dados(PDF) 28 Page - ams AG

Nome de Peças AS8650
Descrição Electrónicos  High-efficient Power Management Device with High-speed CAN Interface
PDF  46 Pages
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Fabricante Electrônico  AMSCO [ams AG]
Página de início  http://www.ams.com
Logo AMSCO - ams AG

AS8650 Folha de dados(HTML) 28 Page - ams AG

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AS8650
Datasheet - Application In form atio n
8 Application Information
Device Interfaces. There are two ways to communicate with AS8650, one is 4 wires SPI and other is I2C. The selection between these two
interfaces is through I2C_EN pin, as shown in Table 15. The pins CS, SCLK, SDI, and SDO are used for SPI interface. For I2C interface, SCLK
is used as I2C Clock and SDA is used as I2C data line. Pins SCLKI2C / SCLKSPI and SDAI2C / SDISPI are multiplexed for both SPI and I2C
interface. Since I2C_EN is a digital input pin, it has to be connected either to VLDO1 or GND.
Note:
I2C_EN should not be changed during a I2C/SPI Read/Write operation. Maximum switching delay between I2C and SPI is 8µs.
8.1 Serial Peripheral Interface
The Serial Peripheral Interface (SPI) provides the communication link with the microcontroller. The SPI is configured for half-duplex data transfer.
The SPI provides access to configuration registers, control registers, and diagnostic registers. The modes of the AS8650 are changed by writing
required code in to mode control register through SPI. The SPI is also used to enter into test and OTP modes. This interface is only slave
interface and only master can initiate SPI operation.
The SPI can work on both the clock polarities. The polarity of the clock depends on the value of SCLK at the falling edge of CS. At the falling
edge of CS if SCLK is “1” then the SPI is positive edge triggered and if the SCLK is “0” then SPI is negative edge triggered logic (see Table 16).
The SPI protocol frame is divided in to two fields, the header field and the data field. The header field is 1 byte long containing a read/write
command bit, 5 address bits and 2 reserved bits. The data field is of one data byte. The SPI frame format is shown in Figure 15. In the data
phase MSB is sent first and LSB is sent last.
Figure 15. SPI Frame Format
Table 15. Device Interface Selection
I2C_EN
Description
LOW
Interface is 4-wire SPI
HIGH
Interface is I2C
Table 16. SPI Clock Polarity
CS
SCLK
Description
LOW
HIGH
Serial data is transferred at falling edge and sampled at rising edge of SCLK
LOW
LOW
Serial data is transferred at rising edge and sampled at falling edge of SCLK
R/W
A0
A1
A2
A3
A4
Header Field
Data Field
1 byte
Reserved
Bits
5 bits
Address
0 – WRITE
1 –
READ
0
0
D7
D6
D5
D4
D3
D2
D1
D0



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