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AS8650

Datasheet - Detailed Descr i p ti on

7.3 State Diagram

Figure 5. State Machine Model

7.4 Initialization Sequence

After this, DCDC converter is switched ON, on receiving PG (power good) signal from DCDC converter, LDO1 regulator is switched ON. If

VLDO1 > VLDO1_POKTH threshold, VLDO1_RESET is generated. After this, active-low PORN_2_OTP is generated. The rising edge of

OTP latch into the pre-regulator domain register. The Reset timeout is also started. The RESET signal is de-asserted after Reset timeout period

mode. If microcontroller misses the trigger, RESET signal is generated and again Reset timeout will start. If microcontroller misses to give the

startup watchdog trigger for 3 consecutive times, then the device enters into Sleep mode. On receiving Normal mode command from

microcontroller, device turns ON the LDO2 and LDO3 regulators. When VLDO2 and VLDO3 reach their respective power-ok (POK) threshold

values, device interrupts microcontroller. The circuit is designed such that the state machine initializes correctly even for very slow ramp rates on

VSUP of the order of 0.5V/min.

Power Off

Normal

Receive Only

Standby

Sleep

Host command (go to ReceiveOnly)

Host command (go to Normal)

Hos

t co

mm

and

(go

to N

orm

al)

Hos

t co

mm

and

(go

to S

tand

by)

OR

Local Wake

Host command (go to Sleep)

Hos

t co

mm

and

(go

to S

leep

)

disabled

disabled

BUS transmitter will be enabled on

From any state

Power-up

VS

UP

_P

OR

_R

ES

ET

==

0

V3p3

POR

timeou

t

OR

startup

watch

dog tim

eout

Standby state

VSUP_UV_flag = 1 OR V5V_UV_flag =1

VSUP_UV_flag =1 OR

disabled