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AS8650

Datasheet - Detailed Descr i p ti on

7.5 DCDC Converter

The high-efficiency, high-voltage, hysteretic step-down DCDC converter, operates in asynchronous mode and delivers 500mA of output load to

drive the three internal LDOs and the CAN Transceiver. The low-power architecture extends hold-up time in battery-backed and critical

applications where maximum up-time over a wide input supply voltage range is needed, while still providing for high efficiencies of up to 90%

during peak current demands.

7.6 Voltage Regulator LDO1

The stability of the voltage output is below ±2.5% over the full input range and temperature for load current up to 100 mA at 3.3V. Power Input to

this LDO is the V5V_LDO1 pin. This LDO is activated in Normal, Receive only or Standby mode. It is switched OFF in Sleep mode.

7.7 Voltage Regulator LDO2

The stability of the voltage output is below ±2.5% over input range and temperature for load current up to 100 mA. The voltage regulator is

programmable between 3.3V and 1.8V via I2C or SPI interface. Power Input to this LDO is the V5V_LDO2 pin. LDO2 is activated in Normal and

Receive Only mode.

7.8 Voltage Regulator LDO3

The stability of the voltage output is below ±2.5% over input range and temperature for load current up to 100 mA. The voltage regulator is

programmable between 3.3V and 1.8V via I2C or SPI interface. Power Input to this LDO is the V5V_LDO3 pin. LDO3 is activated in Normal and

Receive Only mode.

7.9 Over-Temperature Monitor

can be accessed via the I2C and the SPI interface and an interrupt is signalled on INTN pin. The CAN transmitter is disabled and the device

device enters sleep mode irrespective of the current mode and bus wake receiver (Low power receiver) is disabled. As soon as the temperature

7.10 Undervoltage Reset

interrupt at INTN is generated. In this case the device enters into the Stand-by mode. The LDO1 voltage regulator remains activated. Two

scenarios are possible at this stage:

VSUP is recovering: If VSUP exceeds the VSUP_POKTH threshold, the VSUP_POK_flag is set and the device remains in Stand-by mode.

VSUP is still falling: In this case the device continues to stay in Stand-by mode. If voltage falls below VSUP_RESET threshold, then the

device enters Power-Off and the logic is reset.

value, V5V_POK_flag is set. In case a flag is set, an interrupt is generated at the INTN pin. If undervoltage on V5V occurs in Normal or Receive

only modes then CAN Transceiver is disabled and the device remains in its operation mode.

device enters into power-up state while RESET signal is asserted and the voltage regulator is still active. Once the VLDO1_POKTH threshold is

reached, RESET signal is de-asserted after reset timeout period and device enters into Standby mode.

indication is given to microcontroller by setting a bit in interrupt register and giving interrupt on INTN pin. Once VLDO2 returns to

VLDO2_POKTH threshold value, VLDO2_POK_flag is set. An indication is given to microcontroller by setting a bit in interrupt register and giving

interrupt on INTN pin.

indication is given to microcontroller by setting a bit in interrupt register and giving interrupt on INTN pin. Once VLDO3 returns to

VLDO3_POKTH threshold value, VLDO3_POK_flag is set. An indication is given to microcontroller by setting a bit in interrupt register and giving

interrupt on INTN pin.