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DAC1008D650 Folha de dados(PDF) 73 Page - NXP Semiconductors |
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DAC1008D650 Folha de dados(HTML) 73 Page - NXP Semiconductors |
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73 / 98 page ![]() DAC1008D650 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Preliminary data sheet Rev. 1 — 1 October 2010 73 of 98 NXP Semiconductors DAC1008D650 2 ×, 4× or 8× interpolating DAC with JESD204A Table 125. INTR_MISC_ENA register (address 0Fh) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 INTR_ENA_CS_INIT_LN3 R/W 0 intr_misc in case cs_state_ln3 = cs_init 6 INTR_ENA_CS_INIT_LN2 R/W 0 intr_misc in case cs_state_ln2 = cs_init 5 INTR_ENA_CS_INIT_LN1 R/W 0 intr_misc in case cs_state_ln1 = cs_init 4 INTR_ENA_CS_INIT_LN0 R/W 0 intr_misc in case cs_state_ln0 = cs_init 3 INTR_ENA_BUF_ERR_LN3 R/W 0 generate interrupt if ILA_BUF_ERR_LN3 = 1 2 INTR_ENA_BUF_ERR_LN2 R/W 0 generate interrupt if ILA_BUF_ERR_LN2 = 1 1 INTR_ENA_BUF_ERR_LN1 R/W 0 generate interrupt if ILA_BUF_ERR_LN1 = 1 0 INTR_ENA_BUF_ERR_LN0 R/W 0 generate interrupt if ILA_BUF_ERR_LN0 = 1 Table 126. FLAG_CNT_LSB_LN0 register (address 10h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 0 FLAG_CNT_LN0[7:0] R - LSBs of flag_counter lane 0 Table 127. FLAG_CNT_MSB_LN0 register (address 11h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 0 FLAG_CNT_LN0[15:8] R - MSBs of flag_counter lane 0 Table 128. FLAG_CNT_LSB_LN1 register (address 12h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 0 FLAG_CNT_LN1[7:0] R - LSBs of flag_counter lane 1 Table 129. FLAG_CNT_MSB_LN1 register (address 13h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 0 FLAG_CNT_LN1[15:8] R - MSBs of flag_counter lane 1 Table 130. FLAG_CNT_LSB_LN2 register (address 14h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 0 FLAG_CNT_LN2[7:0] R - LSBs of flag_counter lane 2 Table 131. FLAG_CNT_MSB_LN2 register (address 15h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 0 FLAG_CNT_LN2[15:8] R - MSBs of flag_counter lane 2 Table 132. FLAG_CNT_LSB_LN3 register (address 16h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 to 0 FLAG_CNT_LN3[7:0] R - LSBs of flag_counter lane 3 |
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