DAC1008D650 datasheet(53/98 Pages) NXP

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DAC1008D650

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Preliminary data sheet

Rev. 1 — 1 October 2010

53 of 98

NXP Semiconductors

DAC1008D650

×, 4× or 8× interpolating DAC with JESD204A

Table 63.

RST_EXT_FCLK register (address 04h) bit description

Default settings are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0

RST_EXT_FCLK_TIME[7:0]

R/W

3Fh

specifies extension time reset_fclk in fclk periods

Table 64.

RST_EXT_DCLK register (address 05h) bit description

Default settings are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0

RST_EXT_DCLK_TIME[7:0]

R/W

20h

specifies extension time reset_dclk (in dclk-periods)

Table 65.

DCSMU_PREDIVCNT register (address 06h) bit description

Default settings are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0

DCSMU_PREDIVIDER[7:0]

R/W

1Eh

value used by dcsmu predivider (at fclk)

Table 66.

PLL_CHARGETIME register (address 07h) bit description

Default settings are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0

PLL_CHARGE_TIME[7:0]

R/W

32h

PLL charge time

(at fclk/DCSMU_PREDIVIDER[7:0])

Table 67.

PLL_RUN_IN_TIME register (address 08h) bit description

Default settings are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0

PLL_RUNIN_TIME[7:0]

R/W

32h

PLL run in time (at fclk/DCSMU_PREDIVIDER[7:0])

Table 68.

CA_RUN_IN_TIME register (address 09h) bit description

Default settings are shown highlighted.

Bit

Symbol

Access

Value

Description

7 to 0

CA_RUNIN_TIME[7:0]

R/W

04h

clock alignment run in time

(at fclk/DCSMU_PREDIVIDER[7:0])

Table 69.

SET_VCM_VOLTAGE register (address 16h) bit description

Default settings are shown highlighted.

Bit

Symbol

Access

Value

Description

3 to 0

SET_VCM[3:0]

R/W

02h

set lane common-mode voltage (see Table 76)

Table 70.

SET_SYNC register (address 17h) bit description

Default settings are shown highlighted.

Bit

Symbol

Access

Value

Description

6 to 4

SET_SYNC_VCOM[2:0]

R/W

set synchronization transmitter common-mode level

(see Table 77)

2 to 0

SET_SYNC_LEVEL[2:0]

R/W

set synchronization transmitter output level swing

(see Table 78)

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