DAC1008D650 datasheet(21/98 Pages) NXP

Nome de Peças	DAC1008D650

Descrição Electrónicos	Dual 10-bit DAC up to 650 Msps; 2횞, 4횞 or 8횞 interpolating with JESD204A interface

PDF	98 Pages

Scroll/Zoom	100%

Fabricante Electrônico	NXP [NXP Semiconductors]

Página de início	http://www.nxp.com

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DAC1008D650

All information provided in this document is subject to legal disclaimers.

Preliminary data sheet

Rev. 1 — 1 October 2010

21 of 98

NXP Semiconductors

DAC1008D650

×, 4× or 8× interpolating DAC with JESD204A

10.2.6 Frame assembly

DAC1008D650 supports only /F/ = 1, which means that every frame clock period carries

one byte per lane. Frame assembly combines the octet of lane_0 with the two MSB bits of

lane_1 and reassembles the original 10-bit sample. The same is done for lane_2 and

lane_3. Tail bits are dropped.

The frame assembler also handles previously triggered errors.

If scrambling is enabled:

If a nit_err (not-in-table error) or kout_unexp (unexpected control character) occurs in

lane_0 and/or lane_1, the previous 10-bit sample is repeated twice for I (lane_0,

lane_1). The same is done for Q (lane_2, lane_3).

If scrambling is disabled:

If a nit_err (not-in-table error) or kout_unexp (unexpected control character) occurs in

lane_0 and/or lane_1, the previous 10-bit sample will be repeated once for I (lane_0,

lane_1). The same is done for Q (lane_2, lane_3).

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