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DAC1008D650 Folha de dados(PDF) 52 Page - NXP Semiconductors

Nome de Peças DAC1008D650
Descrição Electrónicos  Dual 10-bit DAC up to 650 Msps; 2횞, 4횞 or 8횞 interpolating with JESD204A interface
PDF  98 Pages
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Fabricante Electrônico  NXP [NXP Semiconductors]
Página de início  http://www.nxp.com
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DAC1008D650 Folha de dados(HTML) 52 Page - NXP Semiconductors

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DAC1008D650
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 1 — 1 October 2010
52 of 98
NXP Semiconductors
DAC1008D650
2
×, 4× or 8× interpolating DAC with JESD204A
10.15.2.6
Page 2 bit definition detailed description
Please refer to Table 60 for a register overview and their default values. In the following
tables, all the values emphasized in bold are the default values.
Table 61.
MAINCONTROL register (address 00h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
5
FULL_RE_INIT
R/W
initialization
0
quick reinitialization
1
full reinitialization
4
SYNC_INIT_LEVEL
R/W
synchronization
0
synchronization starts with '0'
1
synchronization starts with '1'
3
-
R/W
must be written with ’0’
2
-
R/W
must be written with ’0’
1
FORCE_RESET_DCLK
R/W
reset_dclk
0
release reset_dclk
1
force reset_dclk
0
FORCE_RESET_FCLK
R/W
reset_fclk
0
release reset_fclk
1
force reset_fclk
Table 62.
JCLK_CNTRL register (address 03h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
Description
7
SR_CDI
R/W
cdi reset
0
no action
1
soft reset cdi
5 to 4
CDI_MODE[1:0]
R/W
cdi mode
00
cdi_mode 0 (^2 modes)
01
cdi_mode 1 (^4 modes)
10
cdi_mode 2 (^8 modes)
11
reserved
2
FCLK_POL
R/W
fclk polarity
0
no action
1
invert polarity
1 to 0
FCLK_SEL[1:0]
R/W
fclk clock source
00
dclk
× 2
01
dclk
10
dclk_div2; running
11
dclk_div2; reset dclk_div2 divider



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