HD64F2149YV datasheet(135/1075 Pages) RENESAS

135 / 1075 page

Section 5 Interrupt Controller

Rev. 3.00 Jan 18, 2006 page 107 of 1044

REJ09B0280-0300

5.2.3

IRQ Enable Register (IER)

IRQ7E

R/W

IRQ6E

R/W

IRQ5E

R/W

IRQ4E

R/W

IRQ3E

R/W

IRQ0E

R/W

IRQ2E

R/W

IRQ1E

R/W

Bit

Initial value

Read/Write

IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests

IRQ7 to IRQ0.

IER is initialized to H'00 by a reset and in hardware standby mode.

Bits 7 to 0—IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits select whether IRQ7 to

IRQ0 are enabled or disabled.

Bit n

IRQnE

Description

IRQn interrupt disabled

(Initial value)

IRQn interrupt enabled

(n = 7 to 0)

5.2.4

IRQ Sense Control Registers H and L (ISCRH, ISCRL)

• ISCRH

IRQ7SCB

R/W

IRQ7SCA

R/W

IRQ6SCB

R/W

IRQ6SCA

R/W

IRQ5SCB

R/W

IRQ4SCA

R/W

IRQ5SCA

R/W

IRQ4SCB

R/W

Bit

Initial value

Read/Write

• ISCRL

IRQ3SCB

R/W

IRQ3SCA

R/W

IRQ2SCB

R/W

IRQ2SCA

R/W

IRQ1SCB

R/W

IRQ0SCA

R/W

IRQ1SCA

R/W

IRQ0SCB

R/W

Bit

Initial value

Read/Write

ISCRH and ISCRL are 8-bit readable/writable registers that select rising edge, falling edge, or

both edge detection, or level sensing, for the input at pins

IRQ7 to IRQ0.

Each of the ISCR registers is initialized to H'00 by a reset and in hardware standby mode.

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