HD64F2149YV datasheet(1006/1075 Pages) RENESAS

1006 / 1075 page

Appendix B Internal I/O Registers

Rev. 3.00 Jan 18, 2006 page 978 of 1044

REJ09B0280-0300

TCSRX—Timer Control/Status Register X

H'FFF1

TMRX

CMFB

R/(W)*

CMFA

R/(W)*

OVF

R/(W)*

ICF

R/(W)*

OS3

R/W

OS0

R/W

OS2

R/W

OS1

R/W

Bit

Initial value

Read/Write

TCSRX

Output select 1 and 0

No change at compare match A

0 output at compare match A

1 output at compare match A

Output inverted at compare

match A (toggle output)

Note:

Output select 3 and 2

No change at compare match B

0 output at compare match B

1 output at compare match B

Output inverted at compare

match B (toggle output)

Input capture flag

[Clearing condition]

When 0 is written in ICF after reading ICF = 1

[Setting condition]

When a rising edge followed by a falling edge is

detected in the external reset signal after the

ICST bit in TCONRI has been set to 1

Timer overflow flag

[Clearing condition]

When 0 is written in OVF after reading OVF = 1

[Setting condition]

When TCNT overflows from H'FF to H'00

Compare match flag A

[Clearing conditions]

• When 0 is written in CMFA after reading CMFA = 1

• When the DTC is activated by a CMIA interrupt

[Setting condition]

When TCNT = TCORA

Compare match flag B

[Clearing conditions]

• When 0 is written in CMFB after reading CMFB = 1

• When the DTC is activated by a CMIB interrupt

[Setting condition]

When TCNT = TCORB

* Only 0 can be written in bits 7 to 4, to clear the flags.

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