HD64F2149YV datasheet(1004/1075 Pages) RENESAS

1004 / 1075 page

Appendix B Internal I/O Registers

Rev. 3.00 Jan 18, 2006 page 976 of 1044

REJ09B0280-0300

TCSR1—Timer Control/Status Register 1

H'FFEA

WDT1

OVF

R/(W)*1

WT/

R/W

TME

R/W

PSS

R/W

RST/

NMI

R/W

CKS0

R/W

CKS2

R/W

CKS1

R/W

Bit

Initial value

Read/Write

TCSR1

Clock select 2 to 0

PSS

Clock

CKS2

CKS1

CKS0

Notes: 1.

φ/2

φ/64

φ/128

φ/512

φ/2048

φ/8192

φ/32768

φ/131072

SUB/2

SUB/4

SUB/8

SUB/16

SUB/32

SUB/64

SUB/128

SUB/256

Reset or NMI

NMI interrupt requested

Internal reset requested

Prescaler select*2

TCNT counts on a ø-based prescaler (PSM) divided clock pulses

TCNT counts on a øSUB-based prescaler (PSS) divided clock pulses

Timer enable

TCNT is initialized to H'00 and halted

TCNT counts

Timer mode select

Interval timer mode: Interval timer interrupt request (WOVI) sent to CPU

when TCNT overflows

Watchdog timer mode: Reset or NMI interrupt request sent to CPU when

TCNT overflows

RESO pin output goes low simultaneously (when internal reset is selected)

Overflow flag

[Clearing conditions]

• When 0 is written in the TME bit

• When 0 is written in OVF after reading TCSR when OVF = 1

[Setting condition]

When TCNT overflows from H'FF to H'00

When internal reset request is selected in watchdog timer mode, OVF is cleared

automatically by an internal reset after being set

Only 0 can be written, to clear the flag.

For operation control when a transition is made to power-down mode, see section 24.2.3, Timer Control/Status Register (TCSR).

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