HD64F2149YV datasheet(922/1075 Pages) RENESAS

Nome de Peças	HD64F2149YV

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

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Appendix B Internal I/O Registers

Rev. 3.00 Jan 18, 2006 page 894 of 1044

REJ09B0280-0300

MRA—DTC Mode Register A

H'EC00–H'EFFF

DTC

SM1

Undefined

—

SM0

Undefined

—

DM1

Undefined

—

DM0

Undefined

—

MD1

Undefined

—

Undefined

—

MD0

Undefined

—

DTS

Undefined

—

Bit

Initial value

Read/Write

DTC data transfer size

0 Byte-size transfer

1 Word-size transfer

DTC transfer mode select

0 Destination side is repeat

area or block area

1 Source side is repeat area

or block area

DTC mode

Normal mode

Repeat mode

Block transfer mode

—

Destination address mode

DAR is fixed

DAR is incremented after a transfer

(by 1 when Sz = 0; by 2 when Sz = 1)

—

DAR is decremented after a transfer

(by 1 when Sz = 0; by 2 when Sz = 1)

Source address mode

SAR is fixed

SAR is incremented after a transfer

(by 1 when Sz = 0; by 2 when Sz = 1)

—

SAR is decremented after a transfer

(by 1 when Sz = 0; by 2 when Sz = 1)

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