HD64F2149YV datasheet(589/1075 Pages) RENESAS

589 / 1075 page

Section 17 Keyboard Buffer Controller

Rev. 3.00 Jan 18, 2006 page 561 of 1044

REJ09B0280-0300

17.1.3

Input/Output Pins

Table 17.1 lists the input/output pins used by the keyboard buffer controller.

Table 17.1

Keyboard Buffer Controller Input/Output Pins

Channel

Name

Abbreviation*

I/O

Function

KBC clock I/O pin (KCLK0)

PS2AC

I/O

KBC clock input/output

KBC data I/O pin (KD0)

PS2AD

I/O

KBC data input/output

KBC clock I/O pin (KCLK1)

PS2BC

I/O

KBC clock input/output

KBC data I/O pin (KD1)

PS2BD

I/O

KBC data input/output

KBC clock I/O pin (KCLK2)

PS2CC

I/O

KBC clock input/output

KBC data I/O pin (KD2)

PS2CD

I/O

KBC data input/output

Note:

These are the external I/O pin names. In the text, clock I/O pins are referred to as KCLK

and data I/O pins as KD, omitting the channel designations.

17.1.4

Table 17.2 lists the registers of the keyboard buffer controller.

Table 17.2

Keyboard Buffer Controller Registers

Channel

Name

Abbreviation

R/W

Initial Value

Address*

Keyboard control register H

KBCRH0

R/(W)*

H'70

H'FED8

Keyboard control register L

KBCRL0

R/W

H'70

H'FED9

Keyboard data buffer register

KBBR0

H'00

H'FEDA

Keyboard control register H

KBCRH1

R/(W)*

H'70

H'FEDC

Keyboard control register L

KBCRL1

R/W

H'70

H'FEDD

Keyboard data buffer register

KBBR1

H'00

H'FEDE

Keyboard control register H

KBCRH2

R/(W)*

H'70

H'FEE0

Keyboard control register L

KBCRL2

R/W

H'70

H'FEE1

Keyboard data buffer register

KBBR2

H'00

H'FEE2

Common

Module stop control register

MSTPCRH

R/W

H'3F

H'FF86

MSTPCRL

R/W

H'FF

H'FF87

Notes: 1. Lower 16 bits of the address.

2. Only 0 can be written in bits 2 and 1, to clear the flags.

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