HD64F2149YV datasheet(389/1075 Pages) RENESAS

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Section 12 8-Bit Timers

Rev. 3.00 Jan 18, 2006 page 361 of 1044

REJ09B0280-0300

12.2.6

Serial/Timer Control Register (STCR)

IICS

R/W

IICX1

R/W

IICX0

R/W

IICE

R/W

FLSHE

R/W

ICKS0

R/W

—

R/W

ICKS1

R/W

Bit

Initial value

Read/Write

STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode

(when the on-chip IIC option is included), and on-chip flash memory and also selects the TCNT

input clock.

For details on functions not related to the 8-bit timers, see section 3.2.4, Serial Timer Control

not used, do not write 1 to the corresponding bit.

STCR is initialized to H'00 by a reset and in hardware standby mode.

Bits 7 to 4—I

2C Control (IICS, IICX1, IICX0, IICE): These bits control the operation of the I2C

bus interface, etc. when the IIC option is included on-chip. See section 3.2.4, Serial Timer Control

2C Bus Interface, for details.

Bit 3—Flash Memory Control Register Enable (FLSHE): Controls the access of CPU to the

flash memory control registers, the power-down mode control registers, and the supporting

module control registers. See section 3.2.4, Serial Timer Control Register (STCR).

Bit 2—Reserved: Do not write 1 to this bit.

Bits 1 and 0—Internal Clock Select 1 and 0 (ICKS1, ICKS0): These bits, together with bits

CKS2 to CKS0 in TCR, select the clock to be input to TCNT. For details, see section 12.2.4,

Timer Control Register (TCR).

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