HD64F2149YV datasheet(388/1075 Pages) RENESAS

Nome de Peças	HD64F2149YV

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

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Fabricante Electrônico	RENESAS [Renesas Technology Corp]

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Section 12 8-Bit Timers

Rev. 3.00 Jan 18, 2006 page 360 of 1044

REJ09B0280-0300

Bits 3 to 0—Output Select 3 to 0 (OS3 to OS0): These bits specify how the timer output level is

to be changed by a compare-match of TCOR and TCNT.

OS3 and OS2 select the effect of compare-match B on the output level, OS1 and OS0 select the

effect of compare-match A on the output level, and both of them can be controlled independently.

Note, however, that priorities are set such that: trigger output > 1 output > 0 output. If compare-

matches occur simultaneously, the output changes according to the compare-match with the higher

priority.

Timer output is disabled when bits OS3 to OS0 are all 0.

After a reset, the timer output is 0 until the first compare-match occurs.

Bit 3

Bit 2

OS3

OS2

Description

No change when compare-match B occurs

(Initial value)

0 is output when compare-match B occurs

1 is output when compare-match B occurs

Output is inverted when compare-match B occurs (toggle output)

Bit 1

Bit 0

OS1

OS0

Description

No change when compare-match A occurs

(Initial value)

0 is output when compare-match A occurs

1 is output when compare-match A occurs

Output is inverted when compare-match A occurs (toggle output)

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