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HD64F2149YV Folha de dados(PDF) 356 Page - Renesas Technology Corp |
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HD64F2149YV Folha de dados(HTML) 356 Page - Renesas Technology Corp |
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356 / 1075 page ![]() Section 11 16-Bit Free-Running Timer Rev. 3.00 Jan 18, 2006 page 328 of 1044 REJ09B0280-0300 External Clock: If external clock input is selected by bits CKS1 and CKS0 in TCR, FRC increments on the rising edge of the external clock signal. The pulse width of the external clock signal must be at least 1.5 system clock ( φ) periods. The counter will not increment correctly if the pulse width is shorter than 1.5 system clock periods. Figure 11.4 shows the increment timing. N + 1 N FRC input clock φ FRC External clock input pin Figure 11.4 Increment Timing with External Clock Source |
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