HD64F2149YV datasheet(350/1075 Pages) RENESAS

Nome de Peças	HD64F2149YV

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1075 Pages

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Fabricante Electrônico	RENESAS [Renesas Technology Corp]

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Section 11 16-Bit Free-Running Timer

Rev. 3.00 Jan 18, 2006 page 322 of 1044

REJ09B0280-0300

Bit 7

IEDGA

Description

Capture on the falling edge of FTIA

(Initial value)

Capture on the rising edge of FTIA

Bit 6—Input Edge Select B (IEDGB): Selects the rising or falling edge of the input capture B

signal (FTIB).

Bit 6

IEDGB

Description

Capture on the falling edge of FTIB

(Initial value)

Capture on the rising edge of FTIB

Bit 5—Input Edge Select C (IEDGC): Selects the rising or falling edge of the input capture C

signal (FTIC).

Bit 5

IEDGC

Description

Capture on the falling edge of FTIC

(Initial value)

Capture on the rising edge of FTIC

Bit 4—Input Edge Select D (IEDGD): Selects the rising or falling edge of the input capture D

signal (FTID).

Bit 4

IEDGD

Description

Capture on the falling edge of FTID

(Initial value)

Capture on the rising edge of FTID

Bit 3—Buffer Enable A (BUFEA): Selects whether ICRC is to be used as a buffer register for

ICRA.

Bit 3

BUFEA

Description

ICRC is not used as a buffer register for input capture A

(Initial value)

ICRC is used as a buffer register for input capture A

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