M32CSLASH8B datasheet(253/406 Pages) RENESAS

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M32C/8B Group

17. Serial Interfaces

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 236 of 385

17.1.4

Special Mode 2

Full-duplex clock synchronous serial communications are allowed in this mode. SS function is used for transmit

and receive control. The input signal to the SSi pin (i = 0 to 4) determines whether the transmit and receive

operation is enabled or disabled. When it is disabled, the output pin is placed in a high-impedance state. Table

17.13 lists specifications of special mode 2. Table 17.14 lists pin settings. Figure 17.27 shows register settings.

Table 17.13

Special Mode 2 Specifications

NOTES:

1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).

2. If an external clock is selected, ensure that an “H” signal is applied to the CLKi pin when the CKPOL bit in the

UiC0 register is set to 0, and that an “L” signal is applied when the CKPOL bit is set to 1.

3. If an overrun error occurs, a read from the UiRB register returns undefined values. The IR bit in the SiRIC

Item

Specification

Data format

Data length: 8 bits long

Baud rate

• The CKDiR bit in the UiMR register (i = 0 to 4) is set to 0 (internal clock):

fj / (2 (m + 1))

fj = f1, f8, f2n(1) m: setting value of the UiBRG register (00h to FFh)

• The CKDIR bit to 1 (external clock): input from the CLKi pin

Transmit/receive control

• SS function

Output pin is placed in a high-impedance state to avoid data conflict between a

master and other masters, or a slave and other slaves.

Transmit and receive

start condition

Internal clock is selected (master mode):

• Set the TE bit in the UiC1 register to 1 (transmit operation enabled)

• The TI bit in the UiC1 register is 0 (data in the UiTB register)

• Set the RE bit in the UiC1 register to 1 (receive operation enabled)

• “H” signal is applied to the SSi pin when the SS function is used

External clock is selected (slave mode)(2):

• Set the TE bit to 1

• The TI bit is 0

• Set the RE bit to 1

• “L” signal is applied to the SSi pin

If transmit-only operation is performed, the RE bit setting is not required in both cases.

Interrupt request

generation timing

Transmit interrupt (The UiIRS bit in the UiC1 register selects one of the following):

• The UiIRS bit is set to 0 (no data in the UiTB register):

when data is transferred from the UiTB register to the UARTi transmit shift register

(transmit operation started)

• The UiIRS bit is set to 1 (transmit operation completed):

when data transmit operation from the UARTi transmit shift register is completed

Receive interrupt:

• When data is transferred from the UARTi receive shift register to the UiRB register

(receive operation completed)

Error detection

• Overrun error(3)

Overrun error occurs when the 7th bit of the next data is received before reading the

UiRB register

• Mode error

Mode error occurs when an “L” signal is applied to the SSi pin in master mode

Selectable function

• CLK polarity

Transmit data output timing and receive data input timing can be selected

• LSB first or MSB first

Data is transmitted or received from either bit 0 or bit 7

• Serial data logic inverse

Transmit and receive data are logically inverted

• TXD and RXD I/O polarity Inverse

The level output from the TXD pin and the level applied to the RXD pin are inverted.

• Clock phase

One of four combinations of serial clock polarity and phase can be selected

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