6

dc2365af

DEMO MANUAL DC2365A

Dc2365a setup

DC Power

The DC2365A requires ±16VDC and draws +80mA/–6mA.

Most of the supply current is consumed by the CPLD,

regulators and discrete logic on the board. The ±16VDC

inputvoltagepowerstheADCthroughLT1763andLT1964

regulators which provide protection against accidental

reverse bias. Additional regulators provide power for the

CPLD and external reference.

Clock Source

You must provide a low jitter 2.5VP-P sine or square wave

to the clock input, J1. The clock input is AC coupled so the

DC level of the clock signal is not important. A generator

such as the Rohde & Schwarz SMB100A high speed clock

source is recommended to drive the clock input. Even a

good generator can start to produce noticeable jitter at low

frequencies.Thereforeitisrecommendedforlowersample

ratestodividedownahigherfrequencyclocktothedesired

sample rate. The ratio of clock frequency to conversion

rate is shown in Table 1. If the clock input is to be driven

with logic, it is recommended that the 49.9Ω termination

resistor (R4) be removed. Driving R4 with discrete logic

may result in slow rising edges. These slow rising edges

may compromise the SNR of the converter in the presence

of high-amplitude higher frequency input signals.

Data Output

Parallel data output from this board (0V to 2.5V default),

if not connected to the DC890, can be acquired by a logic

analyzer,andsubsequentlyimportedintoaspreadsheet,or

mathematical package depending on what form of digital

signal processing is desired. Alternatively, the data can

be fed directly into an application circuit. Use pin 50 of

P1 to latch the data. The data should be latched using the

negative edge of this signal. The data output signal levels

at P1 can also be increased to 0V to 3.3V if the application

circuit requires a higher voltage. This is accomplished by

moving JP2 to the 3.3V position.

Reference

The default reference is the LTC2358-18 internal 4.096V

reference. Alternatively, if a higher reference voltage is de-

sired,theLTC6655-5reference(U7)canbeusedbysetting

the REF jumper (JP1) to the EXT position and installing a

0Ω resistor in the R7 position as shown in Figure 4. This

should result in better SNR performance but may slightly

degrade the THD performance of the LTC2358-18.

V+

5V

C13

1µF

C12

2.2µF

C15

1µF 50V

C11

47µF 10V

1210

X7R

REFIN

REFBUF

19

21

R7

0

REFBUF

REFBUF

E1

DC2365 F04

SHDN

VIN

GND

GND

GND

VOUT_F

VOUT_S

GND

8

7

6

5

1

2

3

4

U7

LTC6655BHMS8-5

1

2

3

INT

EXT

JP1

REF

Figure 4. External Reference Option for DC2365A

Analog Inputs

All eight inputs have the same driver circuitry. An example

of the default driver circuit for the analog inputs of the

LTC2358-18 on the DC2365A is shown in Figure 5. The

circuit of Figure 5 provides a pseudo-differential output to

channel 0 of the LTC2358-18 with a maximum ±10.24V

input voltage. Alternatively, the jumpers for AIN0 at JP5

and J7 can be removed and AIN0 can be driven fully dif-

ferentially externally through a twisted pair cable at the

provided terminals at JP5. Fully differential drive should

provide a slight improvement in THD performance.

DC890 Data Collection

For SINAD, THD or SNR testing, a low noise, low distor-

tion generator such as the B&K Type 1051 or Stanford

Research SR1 should be used. A low jitter RF oscillator

such as the Rohde & Schwarz SMB100A is used to drive

the clock input. This demo board is tested in house by

attempting to duplicate the FFT plot shown in Typical