RA4T1 datasheet(64/89 Pages) RENESAS

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Table 2.35

A/D conversion characteristics for unit 0 (2 of 2)

Conditions: PCLKC = 1 to 50 MHz

Parameter

Min

Typ Max

Unit Test conditions

Channel-dedicated sample-

and-hold circuits not in use

(AN000 to AN002)

Conversion time*1

(operation at PCLKC

= 50 MHz)

Permissible signal

source impedance

Max. = 1 kΩ

0.52

(0.26)*2

—

μs

Sampling in 13

states

Offset error

—

±1.0 ±2.5

LSB —

Full-scale error

—

±1.0 ±2.5

LSB —

Absolute accuracy

—

±2.0 ±4.5

LSB —

DNL differential nonlinearity error

—

±0.5 ±1.5

LSB —

INL integral nonlinearity error

—

±1.0 ±2.5

LSB —

High-precision high-speed

channels

(AN007)

Conversion time*1

(Operation at

PCLKC = 50 MHz)

Permissible signal

source impedance

Max. = 1 kΩ

0.80

(0.54)*2

—

μs

Sampling in 27

states

Offset error

—

±1.0 ±2.5

LSB —

Full-scale error

—

±1.0 ±2.5

LSB —

Absolute accuracy

—

±2.0 ±4.5

LSB —

DNL differential nonlinearity error

—

±0.5 ±1.5

LSB —

INL integral nonlinearity error

—

±1.0 ±2.5

LSB —

High-precision normal-speed

channels

(AN004 to AN006, AN008,

AN011 to AN013)

Conversion time*1

(Operation at

PCLKC = 50 MHz)

Permissible signal

source impedance

Max. = 1 kΩ

0.92

(0.66)*2

—

μs

Sampling in 33

states

Offset error

—

±1.0 ±2.5

LSB —

Full-scale error

—

±1.0 ±2.5

LSB —

Absolute accuracy

—

±2.0 ±4.5

LSB —

DNL differential nonlinearity error

—

±0.5 ±1.5

LSB —

INL integral nonlinearity error

—

±1.0 ±2.5

LSB —

Normal-precision normal-

speed channels

(AN016)

Conversion time*1

(Operation at

PCLKC = 50 MHz)

Permissible signal

source impedance

Max. = 1 kΩ

0.92

(0.66)*2

—

μs

Sampling in 33

states

Offset error

—

±1.0 ±5.5

LSB —

Full-scale error

—

±1.0 ±5.5

LSB —

Absolute accuracy

—

±2.0 ±7.5

LSB —

DNL differential nonlinearity error

—

±0.5 ±4.5

LSB —

INL integral nonlinearity error

—

±1.0 ±5.5

LSB —

Note:

These specification values apply when there is no access to the external bus during A/D conversion. If access occurs during A/D

conversion, values might not fall within the indicated ranges.

The use of PORT0 as digital outputs is not allowed when the 12-Bit A/D converter is used.

The characteristics apply when AVCC0, AVSS0, VREFH0, VREFL0, and 12-bit A/D converter input voltage are stable.

Note 1. The conversion time includes the sampling and comparison times. The number of sampling states is indicated for the test

conditions.

Note 2. Values in parentheses indicate the sampling time.

Table 2.36

A/D internal reference voltage characteristics

Parameter

Min

Typ

Max

Unit

Test conditions

A/D internal reference voltage

1.13

1.18

1.23

—

Sampling time

4.15

—

µs

—

RA4T1 Datasheet

2. Electrical Characteristics

R01DS0415EJ0140 Rev.1.40

May 29, 2026

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