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RA4T1 Folha de dados(PDF) 39 Page - Renesas Technology Corp |
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RA4T1 Folha de dados(HTML) 39 Page - Renesas Technology Corp |
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39 / 89 page ![]() When not switching the source clock: tPcyc × 2 < tACYC should be satisfied. When switching the source clock: tPcyc × 6 < tACYC should be satisfied. Port tPRW Figure 2.19 I/O ports input timing POEG input trigger tPOEW Figure 2.20 POEG input trigger timing Input capture tGTICW Figure 2.21 GPT input capture timing GPT output PCLKD tGTISK Output delay Figure 2.22 GPT output delay skew RA4T1 Datasheet 2. Electrical Characteristics R01DS0415EJ0140 Rev.1.40 May 29, 2026 Page 39 of 89 |
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