TMS320DM647 datasheet(63/182 Pages) TI

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6.3.6

Preserving Boundary-Scan Functionality on DDR2 Memory Pins

6.4 PLL1 Controller

TMS320DM647/TMS320DM648

Digital Media Processor

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SPRS372B – MAY 2007 – REVISED APRIL 2008

Table 6-5. Clock Domain Assignment

SUBSYSTEM

CLOCK DOMAIN

DOMAIN CLOCK SOURCE

FIXED RATIO vs SYSREFCLK

FREQUENCY

DSP Subsystem

CLKDIV1

PLLC1.REFSYSCLK

Peripherals (CLKDIV3 Domain)

CLKDIV3

PLLC1.SYSCLK1

1:3

Emulation/Trace

CLKDIV4 1

PLLC1.SYSCLK2

1:4

Peripherals (CLKDIV6 Domain)

CLKDIV6

PLLC1.SYSCLK3

1:6

Internal EMIFA Clock

CLKDIV4 0

PLLC1.SYSCLK4

1:4(1)

VICP cop_clk/2

CLKDIV4 2

PLLC1.SYSCLK5

1:4

VICP cop_clk

CLKDIV2

PLLC1.SYSCLK6

1:2

(1)

There is a /2 divider in the path of PLLC1.SYSCLK4 so the effective EMIFA clock is PLLC1.SYSCLK4/2. By default the internal EMIFA

Clock is 1:8.

Similarly, when the DDR2 Memory Controller is not used, the DDR_VREF, RSV19, and RSV20 pins can

be connected directly to ground (VSS) to save power. However, this will prevent boundary-scan from

functioning on the DDR2 Memory Controller pins. To preserve boundary-scan functionality on the DDR2

Memory Controller pins, DDR_VREF, RSV11, and RSV12 should be connected as follows:

• DDR_VREF - connect to a voltage of DV

DD18/2. The DVDD18/2 voltage can be generated directly from

the DVDD18 supply using two 1-kΩ resistors to form a resistor divider circuit.

• RSV19 - connect this pin to ground (V

SS) via a 200-Ω resistor.

• RSV20 - connect this pin to the 1.8-V I/O supply (DV

DD18) via a 200-Ω resistor

The primary PLL controller generates the input clock to the C64x+ megamodule (including the CPU) as

well as most of the system peripherals such as the multichannel audio serial ports (McASPs) and the

external memory interface (EMIFA). Figure 6-5 shows a functional block diagram of the PLL Input Clock.

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