TMS320DM647 datasheet(5/182 Pages) TI

5 / 182 page

Contents

TMS320DM647/TMS320DM648

Digital Media Processor

www.ti.com

SPRS372B – MAY 2007 – REVISED APRIL 2008

6.2

Recommended Clock and Control Signal Transition

TMS320DM647/TMS320DM648 Digital Media

Behavior

............................................. 58

Processor

.................................................. 1

6.3

Power Supplies

...................................... 58

1.1

Features

.............................................. 1

6.4

PLL1 Controller

...................................... 63

1.1.1

Trademarks

.......................................... 2

6.5

PLL2 Controller

...................................... 67

1.2

Description

............................................ 2

6.6

Enhanced Direct Memory Access (EDMA3)

1.3

Functional Block Diagram

............................ 4

Controller

............................................ 69

Revision History

............................................... 6

6.7

Reset Controller

..................................... 83

Device Overview

......................................... 7

6.8

Interrupts

............................................ 90

2.1

Device Characteristics

................................ 7

6.9

DDR2 Memory Controller

........................... 94

2.2

CPU (DSP Core) Description

......................... 8

6.10

External Memory Interface A (EMIFA)

............. 108

2.3

C64x+ CPU

.......................................... 11

6.11

Video Port

.......................................... 115

2.4

Memory Map Summary

............................. 12

6.12

VCXO Interpolated Control (VIC)

.................. 123

2.5

Pin Assignments

.................................... 16

6.13

Universal Asynchronous Receiver/Transmitter

2.6

Terminal Functions

.................................. 20

(UART)

............................................. 125

2.7

Device Support

...................................... 34

6.14

Serial Peripheral Interface Port (SPI)

.............. 127

Device Configuration

.................................. 38

6.15

Inter-Integrated Circuit (I2C)

....................... 131

3.1

System Module Registers

........................... 38

6.16

Host-Port Interface (HPI) Peripheral

............... 135

3.2

Bootmode Registers

................................ 38

6.17

Peripheral Component Interconnect (PCI)

......... 146

3.3

Pullup/Pulldown Resistors

........................... 47

6.18

Multichannel Audio Serial Port (McASP)

System Interconnect

................................... 49

Peripheral

.......................................... 150

4.1

Internal Buses, Bridges, and Switch Fabrics

........ 49

6.19

3-Port Ethernet Switch Subsystem (3PSW)

....... 158

4.2

Data Switch Fabric Connections

.................... 49

6.20

Management Data Input/Output (MDIO)

........... 167

4.3

Configuration Switch Fabric

......................... 51

6.21

Timers

.............................................. 168

Device Operating Conditions

........................ 53

6.22

VLYNQ Peripheral

................................. 171

5.1

Absolute Maximum Ratings

........................ 53

6.23

General-Purpose Input/Output (GPIO)

............. 174

5.2

Recommended Operating Conditions

............... 54

6.24

Emulation Features and Capability

................ 175

5.3

Electrical Characteristics

........................... 55

6.25

IEEE 1149.1 JTAG

................................. 177

Peripheral Information and Electrical

Mechanical Data

....................................... 179

Specifications

........................................... 56

7.1

Thermal Data for ZUT

.............................. 179

6.1

Parameter Information

.............................. 56

7.1.1

Packaging Information

............................. 179

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