TMS320DM647 datasheet(62/182 Pages) TI

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6.3.5

Power and Clock Domains

TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372B – MAY 2007 – REVISED APRIL 2008

www.ti.com

The device includes two power domains: the System Domain and the Ethernet Subsystem Domain. Both

of these power domains are always on when the chip is on. Both of these domains are powered by the

CVDD pins of the device.

The primary PLL controller generates the input clock to the C64x+ megamodule as well as most of the

system peripherals such as the multichannel audio serial ports (McASPs) and the external memory

interface (EMIFA). The secondary PLL controller generates interface clocks for the DDR2 memory

controller. The Ethernet Subsystem is clocked through the SerDes module, which takes input from

REFCLKP/N. The primary PLL controller (PLL1 controller) uses the device input clock CLKIN1 and the

secondary PLL controller (PLL2 controller) uses the device input clock CLKIN2.

Table 6-4 provides a listing of the clock domains.

Table 6-4. Power and Clock Domains

POWER DOMAIN

CLOCK DOMAIN

PERIPHERAL/MODULE/USAGE

System Domain

CLKDIV1

C64x+ CPU

System Domain

CLKDIV3

EDMA/SCR

System Domain

CLKDIV3

DDR Subsystem

System Domain

CLKDIV3

Video Port 0

System Domain

CLKDIV3

Video Port 1

System Domain

CLKDIV3

Video Port 2

System Domain

CLKDIV3

Video Port 3

System Domain

CLKDIV3

Video Port 4

System Domain

CLKDIV3

EMIFA

System Domain

CLKDIV6

HPI

System Domain

CLKDIV6

PCI

System Domain

CLKDIV6

VLYNQ

System Domain

CLKDIV6

UART

System Domain

CLKDIV6

I2C

System Domain

CLKDIV6

TIMER 0

System Domain

CLKDIV6

TIMER 1

System Domain

CLKDIV6

TIMER 2

System Domain

CLKDIV6

TIMER 3

System Domain

CLKDIV6

SPI

System Domain

CLKDIV6

McASP

System Domain

CLKDIV6

VIC

System Domain

CLKDIV6

GPIO

System Domain

CLKDIV6

PLL Controller 1

System Domain

CLKDIV6

PLL Controller 2

System Domain

CLKDIV6

Config SCR

System Domain

CLKDIV4 0

Internal EMIFA Clock

System Domain

CLKDIV4 1

Emulation and Trace

System Domain

CLKDIV4 2

VICP cop_clk/2

System Domain

CLKDIV2

VICP cop_clk

Ethernet Subsystem Domain

SerDes TXBCLK

Ethernet Subsystem

The device architecture is divided into the power and clock domains shown in Table 6-5, which further

shows the clock domains and their ratios.

Peripheral Information and Electrical Specifications

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