MS85RS1MTY datasheet(5/43 Pages) RAMXEED

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MS85RS1MTY(AEC-Q100 Compliant)

DS501-00096-1v0-E



STATUS REGISTER

Bit No.

Bit Name

Function

WPEN

Status Register Write Protect

This is a bit composed of nonvolatile memories (FeRAM). WPEN protects

writing to a status register (refer to “ WRITING PROTECT”) relating with

WP input. Writing with the WRSR command and reading with the RDSR

command are possible.

6 to 4



Not Used Bits

These are bits composed of nonvolatile memories, writing with the WRSR

command is possible. These bits are not used but they are read with the

RDSR command.

BP1

Block Protect

This is a bit composed of nonvolatile memory. This defines size of write

protect block for the WRITE command (refer to “ BLOCK PROTECT”).

Writing with the WRSR command and reading with the RDSR command

are possible.

BP0

WEL

Write Enable Latch

This indicates FeRAM Array and status register are writable. The WREN

command is for setting, and the WRDI command is for resetting. With the

RDSR command, reading is possible but writing is not possible with the

WRSR command. WEL is reset after the following operations.

After power ON.

After WRDI command recognition.

After return from DPD mode.

After return from Hibernate mode.

Achieving continuous writing mode, WEL is not reset after following oper-

ations making it possible to execute writing commands continuously.

After WRSR command recognition.

After WRITE command recognition.

After WRSN command recognition.

After SSWR command recognition.

This is a bit fixed to “0”.

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