T15M1024A-100N datasheet(8/13 Pages) TMT

Nome de Peças	T15M1024A-100N

Descrição Electrónicos	128K X 8 LOW POWER CMOS STATIC RAM

PDF	13 Pages

Scroll/Zoom	100%

Fabricante Electrônico	TMT [Taiwan Memory Technology]

Página de início	http://www.tmtech.com.tw

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8 / 13 page

T15M1024A

TM Technology Inc. reserves the right

P. 8

Publication Date: OCT. 2004

to change products or specifications without notice.

Revision:C

WRITE CYCLE 1

( WE Controlled)

WRITE CYCLE 2

( CE Controlled)

NOTES ( WRITE CYCLE ) :

1. A write occurs during the overlap of a low

, a high CE2 and a low WE . A write begins at

the lateat transition among

goes low, CE2 going high and WE going low. A write end at

the earliest transition among

going high, CE2 going low and WE going high. tWP is

measured from the beginning of write to the end of write.

2. tCW is measured from the later of

going low or CE2 going high to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change.

tWHZ

tDW

D IN

tDH

tWR

tAS

tWP

Ad d r es s

CE 2

CE 1

D OU T

tAW

tCW

tOW

Hig h-Z

Hi g h - Z

DO N' T CA R E

U NDE F I NE D

tDW

D IN

tDH

Ad d r es s

CE 1

D OU T

CE 2

H i gh- Z

Hi g h - Z

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