T15M1024A-100N datasheet(7/13 Pages) TMT

Nome de Peças	T15M1024A-100N

Descrição Electrónicos	128K X 8 LOW POWER CMOS STATIC RAM

PDF	13 Pages

Scroll/Zoom	100%

Fabricante Electrônico	TMT [Taiwan Memory Technology]

Página de início	http://www.tmtech.com.tw

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7 / 13 page

T15M1024A

TM Technology Inc. reserves the right

P. 7

Publication Date: OCT. 2004

to change products or specifications without notice.

Revision:C

TIMING WAVEFORMS

READ CYCLE 1

(Address Controlled)

READ CYCLE 2

(Chip Enable Controlled)

Notes (READ CYCLE) :

1. WE are high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition referenced to

VOH or VOL levels.

4. At any given temperature and voltage condition. tHZ (max.) is less than tLZ (min.) both for a given device

and from device to device interconnection.

5. Transition is measured

±200mV from steady state voltage with load. This parameter is sampled and not

100% tested.

6. Device is continuously selected with

=VIL .

DON'T CARE

UNDEFINED

CE 1

OLZ

CE 2

ACE

OHZ

D OUT

tRC

A ddr es s

tOH

tAA

D OU T

Previous Data Valid

Data Valid

T15M1024A-100N Folha de dados(PDF) 7 Page - Taiwan Memory Technology