PPC440GP-3CC400EZ datasheet(74/83 Pages) AMCC

74 / 83 page

440GP – Power PC 440GP Embedded Processor

AMCC

Revision 1.07 – October 4, 2007

Data Sheet

DDR SDRAM Read Operation

The following examples of timing for DDR SDRAM read operations are based on the relationship between the

incoming data and the PLB clock signal. Since the PLB clock cannot be directly observed, the delay of

MemClkOut(0) relative to the PLB clock (TMD) is provided.

The internal Read Clock signal, like MemClkOut0, is derived from the PLB clock and can be delayed relative to the

PLB clock by programming the RDCT and RDCD fields in the SDRAM0_TR1 register. The delay can be

programmed from 0 to 1/2 cycle in steps using RDCT. Setting RDCD results in a 1/2 cycle delay plus the value set

in RDCT. The delay of Read Clock relative to the PLB clock (TRD) shown below assumes the programmable Read

Clock delay is set to zero.

I/O Timing—DDR SDRAM TSD and THD

Notes:

1. TSD and THD are measured under worst case conditions.

2. The time values in the table include 1/4 of a cycle at the indicated clock speed.

3. To obtain adjusted TSD and THD values for lower clock frequencies, subtract 1.875 ns from the values in the table and add

1/4 of the cycle time for the lower clock frequency (e.g., TSD - 1.875 + 0.25TCYC).

Clock Speed (MHz)

Signal Names

Reference Signal

TSD (ns)

THD (ns)

133

MemData00:07, DM0

DQS0

1.375

133

MemData08:15, DM1

DQS1

1.375

133

MemData16:23, DM2

DQS2

1.375

133

MemData24:31, DM3

DQS3

1.375

133

MemData32:39, DM4

DQS4

1.375

133

MemData40:47, DM5

DQS5

1.375

133

MemData48:55, DM6

DQS6

1.375

133

MemData56:63, DM7

DQS7

1.375

133

ECC0:7, DM8

DQS8

1.375

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