PPC440GP-3CC400EZ datasheet(67/83 Pages) AMCC

67 / 83 page

440GP – Power PC 440GP Embedded Processor

AMCC

Revision 1.07 – October 4, 2007

Data Sheet

Internal Peripheral Interface

IICxSClk

15.3

10.2

IICxSDA

15.3

10.2

UARTSerClk

UART0_Rx

UART0_Tx

10.3

7.1

UART0_DCD

UART0_DSR

UART0_CTS

UART0_DTR

10.3

7.1

UART0_RI

UART0_RTS

10.3

7.1

UART1_Rx

UART1_Tx

10.3

7.1

UART1_DSR/CTS

UART1_RTS/DTR

10.3

7.1

Interrupts Interface

IRQ00:12

JTAG Interface

TDI

async

TMS

async

TDO

15.3

10.2

async

TCK

async

TRST

async

I/O Specifications—All Speeds (Sheet 3 of 4)

Notes:

1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.

2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz and

1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time

requirement is 1ns for 66MHz and 2ns for 33MHz.

3. The clock frequency for RMII operation is 50MHz ± 100ppm.

Signal

Input (ns)

Output (ns)

Output Current (mA)

Clock

Notes

Setup Time

(TIS min)

Hold Time

(TIH min)

Valid Delay

(TOV max)

Hold Time

(TOH min)

I/O H

(minimum)

I/O L

(minimum)

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