PPC440GP-3CC400EZ datasheet(53/83 Pages) AMCC

53 / 83 page

440GP – Power PC 440GP Embedded Processor

AMCC

Revision 1.07 – October 4, 2007

Data Sheet

System Interface

SysClk

Main system clock input.

Clock

5V tolerant

3.3V LVTTL

SysErr

Set to 1 when a machine check is generated.

5V tolerant

3.3V LVTTL

SysReset

Main system reset. External logic can drive this bidirectional pin

low (minimum of 16 cycles) to initiate a system reset. A system

reset can also be initiated by software. The signal is implemented

as an open-drain output (two states; 0 or open circuit).

During chip power-up, this signal must be low from the start of VDD

ramp-up until at least 16 SysClk cycles after VDD is stable.

I/O

5V tolerant

3.3V LVTTL

1, 2

TmrClk

Processor timer external input clock.

5V tolerant

3.3V LVTTL

Halt

Halt from external debugger.

5V tolerant

3.3V LVTTL

1, 4

GPIO00:31

General purpose I/O 0 through 10. To access these functions,

software must set DCR register bits.

I/O

5V tolerant

3.3V LVTTL

TestEn

Test Enable.

1.8V CMOS

w/pull-down

RcvrInh

Receiver Inhibit. Active only when TestEn is active.

5V tolerant

3.3V LVTTL

RefVEn

Reference Voltage Enable. Do not connect for normal operation.

Pull up for Boundary Scan Description Language (BSDL) testing.

1.8V CMOS

w/pull-down

DrvrInh1:2

Driver Inhibit. Used for test purposes only. Tie up for normal

operation

5V tolerant

3.3V LVTTL

Signal Functional Description (Sheet 6 of 7)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3k

Ω to 3.3V, 10kΩ to 5V)

3. Must pull down (recommended value is 1k

Ω)

4. If not used, must pull up (recommended value is 3k

Ω to 3.3V)

5. If not used, must pull down (recommended value is 1k

Ω)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

PPC440GP-3CC400EZ Folha de dados(PDF) 53 Page - Applied Micro Circuits Corporation

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