PM7347 datasheet(251/341 Pages) PMC

251 / 341 page

S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

251

Document ID: PMC-1990267, Issue 3

Address

783H

TXCP-50 Test Register 3

784H

TXCP-50 Test Register 4

785H

TXCP-50 Test Register 5

786H-78FH

Reserved

790H

TTB Test Register 0

791H

TTB Test Register 1

792H

TTB Test Register 2

793H-797H

Reserved

798H

RBOC Test Register 0

799H

RBOC Test Register 1

79AH

XBOC Test Register 1

79BH

XBOC Test Register 0

79CH-79FH

Reserved

7A0H

PRGD Test Register 0

7A1H

PRGD Test Register 1

7A2H

PRGD Test Register 2

7A3H

PRGD Test Register 3

7A4H-7FFH

Reserved

Notes

Although writing values into unused register bits has no effect, it is recommended, to ensure software

compatibility with future, feature-enhanced versions of the device, to write unused register bits with logic

zero. Reading back unused bits can produce either a logic one or a logic zero; therefore, unused

Writable test mode register bits are not initialized upon reset unless otherwise noted.

12.1

Test Mode 0 Details

In test mode 0, the S/UNI-JET allows the logic levels on the device inputs to be read through the

microprocessor interface and allows the device outputs to be forced to either logic level through

the microprocessor interface. The IOTST bit in the S/UNI-JET Master Test Register must be set

to logic one to access the device I/O.

To enable test mode 0, the IOTST bit in the S/UNI-JET Master Test Register is set to logic one

and the device should be left in its default state after reset unless otherwise noted. All Test

Reading the address locations shown in Table 28 returns the values on the indicated inputs:

Table 28 Test Mode 0 Input Read Address Locations

Addr

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

40CH

Device_ID

430H

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