PM7347 datasheet(233/341 Pages) PMC

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S/UNI®-JET Data Sheet

Released

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

233

Document ID: PMC-1990267, Issue 3

Bit

Type

Function

Default

Bit 7

R/W

AISOOF

Bit 6

R/W

Reserved

Bit 5

R/W

TPRBS

Bit 4

R/W

Reserved

Bit 3

R/W

TCELL

Bit 2

R/W

LOC_RESET

Bit 1

R/W

FORCELOS

Bit 0

R/W

LINESYSCLK

LINESYSCLK is used to select the high-speed system clock which the TDPR and RDLC

transmit and receive HDLC controllers use as a reference. If LINESYSCLK is set to logic

one, then the RDLC uses the receive line clock (RCLK[x]) and the TDPR uses the transmit

line clock (TICLK[x]) as its high-speed system reference clock respectively. If

LINESYSCLK is set to logic zero, the RDLC uses the receive ATM Utopia interface clock

(RFCLK) and the TDPR uses the transmit ATM Utopia interface clock (TFCLK) as its high-

speed system reference clock respectively.

The read/write access rate to the RDLC and TDPR are limited by their high-speed reference

clock frequency. Data and Configuration settings can be written into the TDPR at a maximum

rate equal to 1/8 of its high-speed reference clock frequency. Data and status indications can

be read from the TDPR at a maximum rate equal to 1/8 of its high-speed reference clock

frequency. Data and status indications can be read from the RDLC at a maximum rate equal

to 1/10 of its high-speed reference clock frequency.

Instantaneous variations in the high-speed reference clock frequencies (e.g. jitter in the

receive line clock) must be considered when determining the procedure used to read and

write the TDPR and RDLC Registers.

FORCELOS

FORCELOS is used to force a LOS condition on the transmit unipolar or bipolar data outputs

TPOS/TDATO[x] and TNEG[x]. When FORCELOS is logic one, the TPOS/TDATO[x] and

TNEG[x] outputs will be forced to logic zero. When FORCELOS is logic zero, the

TPOS/TDATO[x] and TNEG[x] outputs will operate normally.

LOC_RESET

LOC_RESET performs a software local reset of the corresponding quadrant of the S/UNI-

JET . When LOC_RESET is logic one, the corresponding quadrant of the S/UNI-JET is held

in a reset state. When LOC_RESET is logic zero, the quadrant is in normal operational mode.

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