FDC37C669 datasheet(6/164 Pages) SMSC

6 / 164 page

DESCRIPTION OF PIN FUNCTIONS

QFP/

TQFP

PIN NO.

NAME

SYMBOL

BUFFER

TYPE

DESCRIPTION

HOST PROCESSOR INTERFACE

48-51

53-56

Data Bus 0-7

D0-D7

I/O24

The data bus connection used by the host

microprocessor to transmit data to and from

the chip.

These pins are in a high-

impedance state when not in the output

mode.

nI/O Read

nIOR

This active low signal is issued by the host

microprocessor to indicate a read operation.

nI/O Write

nIOW

This active low signal is issued by the host

microprocessor to indicate a write operation.

Address Enable

AEN

Active high Address Enable indicates DMA

operations on the host data bus.

Used

internally to qualify appropriate address

decodes.

28-34

41-43,

I/O Address

A0-A10

These host address bits determine the I/O

address to be accessed during nIOR and

nIOW cycles.

These bits are latched

internally by the leading edge of nIOR and

nIOW. All internal address decodes use the

full A0 to A10 address bits.

21,52,

DMA Request

A, B, C

DRQ_A

DRQ_B

DRQ_C

O24

This active high output is the DMA request

for byte transfers of data between the host

and the chip. This signal is cleared on the

last byte of the data transfer by the nDACK

signal going low (or by nIOR going low if

nDACK was already low as in demand

mode).

22,36,

nDMA

Acknowledge

A, B, C

nDACK_A

nDACK_B

nDACK_C

An active low input acknowledging the

request for a DMA transfer of data between

the host and the chip.

This input enables

the DMA read or write internally.

Terminal Count

This signal indicates to the chip that DMA

data transfer is complete.

TC is only

accepted when nDACK_x is low. In AT and

PS/2 model 30 modes, TC is active high

and in PS/2 mode, TC is active low.

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