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FDC37C669 Folha de dados(PDF) 13 Page - SMSC Corporation |
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FDC37C669 Folha de dados(HTML) 13 Page - SMSC Corporation |
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13 / 164 page ![]() 13 DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP PIN NO. NAME SYMBOL BUFFER TYPE DESCRIPTION 63-66 68-71 Port Data PD0-PD7 I/O24 The bi-directional parallel data bus is used to transfer information between CPU and peripherals. 100 IOCHRDY IOCHRDY OD24P In EPP mode, this pin is pulled low to extend the read/write command. This pin has an internal pull-up. IDE/ALT IR PINS 24 nIDE Enable Interrupt Request H nIDEEN IRQ_H O24P (Note 1) 024 OD24 This active low signal is active when the IDE is enabled and the I/O address is accessing an IDE register. The interrupt request from a logical device or IRQIN may be output on the IRQH signal. Refer to the configuration registers for more information. If EPP or ECP Mode is enabled, this output is pulsed low, then released to allow sharing of interrupts. 25 nIDE Chip Select 0 IRRX2 nHDCS0 IRRX2 O24P (Note 1) I This is the Hard Disk Chip select corresponding to the eight control block addresses. Alternate IR Receive input 26 nIDE Chip Select 1 IR Transmit 2 nHDCS1 IRTX2 O24P (Note 1) O24P This is the Hard Disk Chip select corresponding to the alternate status register. Alternate IR transmit output MISCELLANEOUS 20 CLOCK 14 CLK14 ICLK The external connection to a single source 14.318 MHz clock. |
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