FDC37C669 datasheet(21/164 Pages) SMSC

21 / 164 page

STATUS REGISTER B (SRB)

Address F1 READ ONLY

This register is read-only and monitors the state

of several disk interface pins, in PS/2 and Model

30 modes. The SRB can be accessed at any

time when in PS/2 mode. In the PC/AT mode

the data bus pins D0 - D7 are held in a high

impedance state for a read of address 3F1.

PS/2 Mode

BIT 0 MOTOR ENABLE 0

Active high status of the MTR0 disk interface

output pin. This bit is low after a hardware reset

and unaffected by a software reset.

BIT 1 MOTOR ENABLE 1

Active high status of the MTR1 disk interface

output pin. This bit is low after a hardware reset

and unaffected by a software reset.

BIT 2 WRITE GATE

Active high status of the WGATE disk interface

output.

BIT 3 READ DATA TOGGLE

Every inactive edge of the RDATA input causes

this bit to change state.

BIT 4 WRITE DATA TOGGLE

Every inactive edge of the WDATA input causes

this bit to change state.

BIT 5 DRIVE SELECT 0

Reflects the status of the Drive Select 0 bit of

the DOR (address 3F2 bit 0). This bit is cleared

after a hardware reset, it is unaffected by a

software reset.

BIT 6 RESERVED

Always read as a logic "1".

BIT 7 RESERVED

Always read as a logic "1".

DRIVE

SEL0

WDATA

TOGGLE

RDATA

TOGGLE

WGATE

MOT

EN1

MOT

EN0

RESET

COND.

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