CC1010-RTR1 datasheet(28/152 Pages) TI

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CC1010

SWRS047

Page 28 of 152

15.6 Interrupts

CC1010 there are a total of 15 interrupt

sources, which share 12 interrupt lines.

These are all shown in Table 13. Each

interrupt’s natural priority, interrupt vector,

interrupt enable and interrupt flag, is also

shown in the table, and will be described

below.

Interrupt

Natural

Priority

Control

Interrupt

Vector

Interrupt

Enable

Interrupt Flag

Flash / Debug interrupt

0x33

EICON.

FDIE

EICON.

FDIF

External Interrupt 0

IP.PX0

0x03

IE.EX0

TCON.IE0 (*)

Timer 0 Interrupt

IP.PT0

0x0B

IE.ET0

TCON.TF0 (*)

External Interrupt 1

IP.PX1

0x13

IE.EX1

TCON.IE1 (*)

Timer 1 Interrupt

IP.PT1

0x1B

IE.ET1

TCON.TF1 (*)

Serial Port 0 Transmit Interrupt

SCON0.TI_0

Serial Port 0 Receive Interrupt

IP.PS0

0x23

IE.ES0

SCON0.RI_0

Serial Port 1 Transmit Interrupt

SCON1.TI_1

Serial Port 1 Receive Interrupt

IP.PS1

0x3B

IE.ES1

SCON1.TI_1

RF Transmit / Receive Interrupt

EIP.PRF

0x43

EIE.RFIE

EXIF.RFIF

Timer 2 Interrupt

EIP.PT2

0x4B

EIE.ET2

EXIF.TF2

ADC Interrupt

EIE.ADIE

and

ADCON2.

ADCIE

EXIF.ADIF

and

ADCON2.

ADCIF

DES Encryption / Decryption

Interrupt

EIP.PAD

0x53

EIE.ADIE

and

CRPCON.

CRPIE

EXIF.ADIF

and

CRPCON.

CRPIF

Timer 3 Interrupt

EIP.PT3

0x5B

EIE.ET3

EXIF.TF3

Realtime Clock Interrupt

EIP.PRTC

0x63

EIE.RTCIE

EICON.RTCIF

(*) - Interrupt flag is cleared by hardware.

Table 13.

CC1010 Interrupt overview

15.6.1

Interrupt Masking

IE.EA is the global interrupt enable for all

interrupts, except the Flash / Debug

interrupt. When IE.EA is set, each

interrupt is masked by the interrupt enable

bits listed in Table 13. When IE.EA is

cleared, all interrupts are masked, except

the Flash / Debug interrupt, which has its

own interrupt mask bit, EICON.FDIE.

15.6.2

Interrupt Processing

When an enabled interrupt occurs, the

CPU jumps to the address of the interrupt

service routine (ISR) associated with that

interrupt, as shown in Table 13. Most

interrupts can also be initiated by setting

the associated interrupt flag from software.

CC1010 executes the ISR to completion

unless another interrupt set at a higher

interrupt level occurs. Each ISR ends with

a RETI (return from interrupt) instruction.

After executing the RETI, CC1010 returns

to the next instruction that would have

been executed if the interrupt had not

occurred.

CC1010 always completes the instruction in

progress before servicing an interrupt. If

the instruction in progress is RETI, or a

write access to any of the IP, IE, EIP, or

EIE

SFRs,

CC1010

completes

one

additional instruction before servicing the

interrupt.

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