CC1010-RTR1 datasheet(43/152 Pages) TI

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CC1010

SWRS047

Page 43 of 152

FLADR (0xAE) - Flash Write Address Register

Bit

Name

R/W

Reset value

Description

7:0

FLADR(7:0)

R/W

0x00

The number of of the Flash page to be written (8 MSB

of the byte address)

FLCON (0xAF) - Flash Write Control Register

Bit

Name

R/W

Reset value

Description

Reserved, read as 0

6:5

FLASH_LP

(1:0)

R/W

Flash Low Power control bits

00 : The Flash module is always active.

01 : The Flash module enters standby mode when the

8051 is put in Idle mode or Stop mode

10 : The Flash module enters standby mode between

instruction fetches and when the 8051 is put in Idle

Mode or Stop Mode.

11 : Reserved for future use.

WRFLASH

R/W

Write Flash Start bit

Starting a Flash page programming is done by first

setting this bit and then setting the 8051 in Idle Mode.

If the

WRFLASH bit is cleared before Idle Mode is

entered, no programming is performed.

3:0

RMADR(3:0)

R/W

0x0

RAM Buffer address

RMADR(3:0) contains the 4 most significant bits of

the RAM address where the data is buffered before

writing to Flash

FLTIM (0xDD) - Flash Write Timing Register

Bit

Name

R/W

Reset value

Description

7:0

FLTIM(7:0)

R/W

0x0A

Flash Write Timing control

FLTIM must be set as described in this section prior

to using the 8051 Flash programming.

If an attempt is made to write data to a

Flash page which is locked (see the

previous section), a Flash / Debug

interrupt will be generated immediately

after Idle Mode is entered. No data will be

written.

It is not possible to read or write the Flash

lock bits from the 8051.

15.13.1 Example Code

Example C code writing data buffered at

address 0x100-0x17F in external RAM to

the second page in Flash (address 0x080-

0x0FF) is shown below. The system clock

frequency is assumed to be 3.6864 MHz.

An interrupt service routine must be

present at address 0x33, which clears the

interrupt flag EICON.FDIF and returns

from the interrupt (RETI).

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