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AT89LS53 Folha de dados(PDF) 29 Page - ATMEL Corporation |
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AT89LS53 Folha de dados(HTML) 29 Page - ATMEL Corporation |
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29 / 35 page ![]() 29 0851C–MICRO–3/06 AT89LS53 Serial Port Timing: Shift Register Mode Test Conditions The values in this table are valid for VCC = 2.7V to 6V and Load Capacitance = 80 pF. Symbol Parameter 12 MHz Oscillator Variable Oscillator Units Min Max Min Max tXLXL Serial Port Clock Cycle Time 1.0 12tCLCL µs tQVXH Output Data Setup to Clock Rising Edge 700 10tCLCL - 133 ns tXHQX Output Data Hold After Clock Rising Edge 50 2tCLCL - 117 ns tXHDX Input Data Hold After Clock Rising Edge 0 0 ns tXHDV Clock Rising Edge to Input Data Valid 700 10tCLCL - 133 ns Shift Register Mode Timing Waveforms AC Testing Input/Output Waveforms (1) Notes: 1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing mea- surements are made at VIH min. for a logic 1 and VIL max. for a logic 0. Float Waveforms (1) Notes: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded VOH/VOL level occurs. |
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